Organic underlayers that improve the performance of organic semiconductors

ABSTRACT

A process for producing high performance organic thin film transistors in which the molecules in the organic thin film are highly ordered and oriented to maximize the mobility of current charge carriers. The uniform monolayer surface over various substrate materials so formed, result in a more reproducible and readily manufacturable process for higher performance organic field effect transistors that can be used to create large area circuits using a range of materials.

FIELD OF THE INVENTION

[0001] The present invention relates generally to the fabrication of electronic devices using organic semiconductors, and more particularly to the use of organic monolayers with specific molecular geometries to modify the substrate surface and improve the performance of subsequently vapor deposited organic semiconductors such as pentacene.

BACKGROUND OF THE INVENTION

[0002] Organic thin films (OTFs) have attracted considerable research interest due to their potential use as a replacement for other, more expensive semiconducting materials. Several organic materials, especially highly conjugated molecules that readily form molecular crystals such as pentacene and sexithiophene, have demonstrated semiconducting properties that approach those of amorphous silicon (Jackson, T. N., et.al., IEEE J. of Selected Topics in Quantum Elect., Vol. 4, No. 1, January/February 1998). Other superior characteristics, such as mechanical flexibility, availability of room or low temperature deposition processes, and compatibility with inexpensive flexible substrate materials make the organic semiconductors viable replacements for amorphous silicon, especially in low cost and large area applications (Dimitrakopoulos, et.al., Science, Vol. 283, 283, 1999). These characteristics make organic thin films suitable candidates for use in thin film transistors (TFTs) for active matrix liquid crystal displays (AMLCD), low speed logic and radio frequency applications such as active tags or smart cards.

[0003] The electrical performance of the OTFs at room temperature is believed to be dominated by the difficulty of moving charge carriers from one molecule to the next because of disorder, defects, and chemical impurities which can form trapping sites within the film (Garnier, F., et.al., J. Am. Chem. Soc., Vol. 115, 8716, 1993). It is generally accepted that increased ordering of the molecules in the OTF, especially in the first few monolayers deposited onto the substrate, will improve the mobility of charge carriers in the film.

[0004] The deposition conditions as well as the state of the substrate surface onto which the pentacene is deposited can have significant influence on the ordering and crystallinity of vapor deposited pentacene. Substrate temperature and deposition rate have been shown to affect the structure and size of the deposited pentacene crystals and the mobility of the deposited film (Dimitrakopoulos, C., et.al., J. Appl. Phys., Vol. 80, 2501, 1996; Gundlach, et.al, IEEE Electron Device Lett., Vol 18, No. 3, March 1997). Surface roughness has been shown to adversely affect the size of pentacene crystals (H. Klauk, et.al., IEEE Trans on Electron Devices, Vol. 46, No 6., June 1999).

[0005] A technique that has been reported in the literature to achieve improved pentacene deposition and electrical performance is the use of self-assembled monolayers (SAMs) of alkyl silanes (such as octadecyltrichlorosilane) on silicon dioxide or glass surfaces deposited either from solution or vapor phase (Lin, Y -Y, et.al., IEEE Electron Device Letters, Vol. 18, No. 12, December 1997; Gundlach, D. J., et.al., Tech. Dig. Intl. Devices Meeting, 1999; Kane, M. G., et.al., IEEE Electron Device Letters, Vol. 21, No. 11, November 2000) or alkyl thiols such as hexadecanethiol (Dimitrakopoulos, C., et.al., U.S. Pat. No. 6,335,539B1) or 2-mercapto 5-nitrobenzimidazole (Wang, J., et.al., 41st Electronic Materials Conf., June 1999) on metal contact surfaces such as gold. Other self-assembled monolayers have not been investigated in the literature to further understand or elaborate on the influence that each monolayer has on the orientation and ordering of the pentacene film during deposition.

SUMMARY OF THE INVENTION

[0006] One object of the present invention is to provide a process for producing high performance organic thin film transistors in which the molecules in the organic thin film are highly ordered and oriented to maximize the mobility of charge carriers.

[0007] Another object of this invention is to provide a uniform monolayer surface over various materials that will result in a more reproducible and readily manufacturable process for higher performance organic field effect transistors that can be used to create large area circuits using a range of materials.

[0008] Other objects of the present invention include:

[0009] (I) To provide a process that operates on common gate dielectrics that are compatible with organic semiconductors, such as silicon dioxide or aluminum oxide.

[0010] (II) To provide a process that operates on common high work function metals that are compatible with organic semiconductors, namely gold and platinum.

[0011] (III) To provide a process that operates at or near room temperature.

[0012] (IV) To provide a process that operates independently of the substrate used permitting, for example, the use of organic substrates.

[0013] (V) To provide a process that improves the performance of the devices at all scales, including very short channel lengths.

[0014] These and other objects and advantages can be achieved by utilizing the present method which includes a step of treating all exposed surfaces of the transistor structure with compounds under conditions effective in forming self-assembled monolayers (SAM) of molecules with specific chemical and geometric structures. It is noted that this may require treatment of the substrate with more than one compound to create SAMs on varying materials. It is also noted that the formation of the self-assembled monolayers of the present invention is carried out prior to deposition of the organic semiconductor.

[0015] Specifically, the method of the present invention comprises the steps of:

[0016] A) 1.) Forming a substrate for organic semiconductor deposition;

[0017] 2.) Depositing a gate electrode on this substrate and patterning it;

[0018] 3.) Depositing a gate insulator;

[0019] 4.) Depositing and patterning the source and drain electrodes;

[0020] 5.) Treating all exposed surfaces with compounds that will form appropriate self-assembled monolayers using molecules described hereinafter;

[0021] 6.) Depositing the organic semiconductors. or,

[0022] B) 1.) Forming a substrate for organic semiconductor deposition;

[0023] 2.) Depositing a gate electrode on this substrate and patterning it;

[0024] 3.) Depositing a gate insulator;

[0025] 4.) Treating the gate insulator with compounds that will form appropriate self-assembled monolayers using molecules described hereinafter;

[0026] 5.) Depositing the organic semiconductor;

[0027] 6.) Depositing and patterning the source and drain electrodes. or,

[0028] C) 1.) Forming a substrate for organic semiconductor deposition;

[0029] 2.) Depositing and patterning the source and drain electrodes;

[0030] 3.) Treating all exposed surfaces with compounds that will form appropriate self-assembled monolayers using molecules described hereinafter;

[0031] 4.) Depositing the organic semiconductors;

[0032] 5.) Depositing a gate insulator;

[0033] 6.) Depositing and patterning a gate on the gate insulator.

[0034] For treating all exposed surfaces with compounds that will form appropriate self-assembled monolayers use molecules having the general formula:

RZ or RZ₂

[0035] and a basic structure related to those depicted in FIG. 1a, wherein Z is a chemical group that will bind to either the substrate or gate insulator (such as a chlorosilane) or the source and drain electrodes (such as a thiol), and R is an organic structure with either a saturated or unsaturated cycloaliphatic or aromatic ring system terminating the molecule such that the terminal bond on the molecule is parallel to the substrate surface, as depicted in the drawing.

[0036] The specific structure of the R group promotes improved ordering of subsequently deposited organic semiconductors, such as pentacene, perhaps by producing a surface similar to a pentacene crystal surface. Monolayers formed from molecules with ring systems terminating in bonds that are parallel to the surface result in organic semiconductor films with consistently improved electrical performance compared to semiconductor layers formed on monolayers with other chemical or geometric structures, or when no monolayer is used.

BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The particular features and advantages of the present invention as well as other objects of the invention will become apparent from the following description taken in connection with the accompanying drawings in which:

[0038] FIGS. 1(a)-(b) depicts typical or generic structures for monolayer-forming molecules disclosed herein. Specifically, FIG. 1a represents the basic structure for self-assembling molecules to be deposited on organic or oxide surfaces where Z can be a silane, germanium halide, carboxylic acid or phosphonic acid. FIG. 1b represents the basic structure for self-assembling molecules to be deposited on metals through interaction with the thiol functional group.

[0039]FIG. 2 is a cross-sectional view of a thin film transistor (TFT) structure, herein referred to as a “top contact” TFT, formed using the process of the present invention with the organic semiconductor deposited on the surface of the gate insulator.

[0040]FIG. 3 is a cross-sectional view of an alternative TFT structure, herein referred to as a “bottom contact” TFT, formed using the process of the present invention with the organic semiconductor deposited on the surfaces of both the gate insulator and the source/drain electrodes.

[0041]FIG. 4 is a cross-sectional view of yet another alternative TFT structure that can be formed using the process of the present invention with the organic semiconductor deposited on the surfaces of the substrate and the source/drain electrodes. The gate insulator and gate electrode are deposited onto the semiconductor.

[0042] FIGS. 5 (a)-(j) include depictions of some of the organic groups that can be used to replace “R” in the generic RZ or RZ₂ formula for species forming self-assembled monolayers.

[0043] FIGS. 6 (a)-(e) includes X-ray diffraction data collected from films of pentacene deposited on various self-assembled monolayers.

[0044] FIGS. 7 (a)-(h) includes Atomic Force Microscope (AFM) micrographs of the pentacene surface topology and crystal size for pentacene deposited on various self-assembled monolayers.

DETAILED DESCRIPTION OF THE INVENTION

[0045] The present invention which provides a method of forming high performance organic thin film transistors and other like circuitry will now be described in more detail by referring to the drawings that accompany the present application. It is noted that the term “thin film”, when used in conjunction with the organic semiconductor material, denotes a film having a thickness of 5 micrometers (5 μm) or less. The term “thin film” is used to distinguish the organic layer used as the semiconducting layer from bulk material, most often used in single crystalline form.

[0046] Reference is first made to FIG. 2 which illustrates one possible TFT structure that can be produced using the process of the present invention. Specifically, the structure shown in FIG. 2 comprises a substrate 10 having a gate 12 formed on an exposed surface of substrate 10. The structure shown in FIG. 2 also comprises a gate insulator 14 that is formed on top of gate 12 and on any remaining exposed areas of substrate 10. It is noted that the gate insulator and the gate make up the gate region of the structure.

[0047] The organic thin film semiconductor 16 is deposited onto the gate insulator, and the source/drain electrodes 20 are deposited on top of the organic semiconductor. A key element of FIG. 2 is that a self-assembled monolayer 18 of the present invention is present on the gate insulator. The presence of self-assembled monolayers on the surface of the gate insulator with specific chemical structures improves the performance of the transistor. Without wishing to be bound by any explanation or theory, it is believed by the applicants' that the self-assembled monolayer of the present invention changes the behavior of the surface to which it is bound in a way that encourages the self-assembly of the organic semiconductor material into a more ordered system. It is believed that the orientation of the terminal aromatic or cyclic aliphatic group can be geometrically arranged in a similar fashion to that of the interfacial layer of pentacene molecules in a thin film molecular crystal, which is known from X-ray data to have the primary (long) axis of the molecule nearly perpendicular to the surface, resulting in the molecule oriented with its terminal carbon-carbon bond essentially parallel to the substrate. By matching the geometric structure of the monolayer surface to that predicted for pentacene thin films, it is expected that the ordering and orientation of subsequently deposited molecules will be enhanced more than for monolayers with other terminal groups. This behavior has not been suggested nor demonstrated in the prior art.

[0048] Suitable substrates that can be employed in the present invention include, but are not limited to: Si-containing substrates such as Si, SiO₂, SiGe, silicon-on-insulators and glass and Al-containing substrates such as sapphire; organic materials, especially those containing hydroxyl or phenolic functionality, interconnect structures and metal layers, and mixtures thereof. The substrate may also be a circuit board or laminate. A highly preferred substrate is a Si wafer (heavily doped) in which a thermally grown SiO₂ layer is present therein. This substrate is highly preferred since the SiO₂ region serves as a common gate.

[0049] The substrate may contain various active device regions and/or isolation regions either on the surface thereof or in the substrate itself. For example, the substrate may contain source/drain regions, shallow trench isolation regions, field oxide regions, metallization layers, dielectric layers and other like layers that are typically present in transistor structures.

[0050] Gate 12 is composed of a conventional gate conductor that is well known to those skilled in the art. For example, the gate can be composed of a conductive metal such as aluminum, tungsten, copper, or chromium, or alternatively, doped single crystalline Si or polysilicon can be used as the gate conductor or an organic conductor such as polyaniline or heavily doped organic semiconductor such as polythiophene. Of these gate materials, a gate comprising n-doped single crystalline Si is highly preferred herein. The gate is formed by first depositing or growing the gate material and then patterning the same using conventional lithography and etching. Conventional deposition processes that can be used in forming the gate include, but are not limited to: chemical vapor deposition, plasma-assisted chemical vapor deposition, sputtering, evaporation or other like deposition processes may be employed. When polysilicon or single crystal Si is used, the doping may take place during the deposition process using an in-situ process, or after using ion implantation and annealing.

[0051] Gate insulator 14 is comprised of conventional dielectric materials well known to those skilled in the art. Preferable gate insulators include inorganic oxide dielectric materials such as SiO₂, Al₂O₃, tantalum pentoxide, barium zirconate titanate, barium strontium titanate, and other like inorganic materials. Other insulating materials, including organic dielectric materials such as polyimide, polyamide, parylene, polymethylmethacrylate and other like organic materials, or inorganic materials such as Si₃N₄ or perovskite-type oxides or other like inorganic materials may be used with slight surface modification to produce hydroxyl functionality on the insulator surface. The gate insulator is formed using conventional processes well known to those skilled in the art, including any of the previously mentioned deposition processes used in forming the gate. SiO₂ is highly preferred in the present invention.

[0052] Electrodes 20 are composed of the same or different conductive metal, metal alloy, metal oxide or metal oxide alloy that contains at least one metal that is highly conductive. Such conductive metals are well known to those skilled in the art and include, for example, platinum (Pt), palladium (Pd), aluminum (Al), gold (Au), tungsten (W), chromium (Cr) or titanium (Ti). The electrodes may be single layered, but preferably the electrodes comprise a stack of two or more metal layers, i.e. a metal stack of Cr and Au, with Au on top, or Ti and Pt, with Pt on top. It is highly preferred that a high work function metal is in proximity to the organic complexes so that carrier injection is facilitated. The electrode (unpatterned) is formed using conventional deposition processes such as evaporation, chemical vapor deposition, plasma-assisted chemical vapor deposition and sputtering, and a patterned electrode is provided by conventional lithography and etching. Alternatively, a shadow mask may be used in forming the patterned electrodes.

[0053] Organic semiconductor 16 is a material including, but not limited to: pentacene, tetracene, and other fused ring structures. Of these materials, pentacene is preferred in the present invention. As stated above, the organic semiconducting material is a thin film material having a thickness of about 5 μm or less. More preferably, the organic semiconducting material has a thickness of from about 100 to about 1000 Å.

[0054] The organic semiconducting material is formed using conventional deposition processes that are well known in the art. For example, the organic semiconducting material is formed by molecular beam deposition, vacuum evaporation, sublimation, spin coating, dip coating, and other like deposition processes. Of these deposition processes, it is highly preferred that the organic semiconducting material be formed by molecular beam deposition in a high vacuum of less than 1×10⁻⁶ torr.

[0055] As mentioned above, the structure of FIG. 2 (as well as FIGS. 3 and 4) include one or more self-assembled monolayers, 18 and 22, that are formed on the surfaces of the insulator or substrate (18) and on the electrodes (22) prior to deposition of the organic thin film semiconductor. The self-assembled monolayers of the present invention comprise compounds having the formula:

RZ or RZ₂

[0056] and a basic structure related to FIG. 1a wherein the “head group”, or reactive group (Z), is a group capable of binding through covalent bonding or strong chemical interactions to the desired surfaces. Desired head groups include but are note limited to: silanes, such as mono, di, or trichlorosilanes, trimethoxysilanes, or triethoxysilanes; germanium halides including mono, di or trichlorogermane, and mono, di, or tribromogermane; phosphonic acids; carboxylic acids, and thiols. Silanes are preferred attachment groups for SiO₂, or organic substrates that contain hydroxyl functionality, such as epoxy resins, although germaniumhalides are also applicable to these substrates. Phosphonic acids and carboxylic acids are preferred attachment groups for other oxide surfaces, such as aluminum oxide. Thiols are the preferred attachment groups for metals such as gold, silver, copper, and platinum.

[0057] The organic R group contains an aromatic, or a saturated or unsaturated, homo or heterocyclic, cycloaliphatic group. The parallel orientation of the external terminal bond in the aromatic or cycloaliphatic group relative to the substrate, as depicted in FIGS. 1 and 5, is one of the key disclosures of this invention.

[0058] FIGS. 5 (a) and (b) specify heterocyclic rings with silyl groups as part of the ring structure, although other similar atoms, such as germanium could be used in place of silicon. The identity of Z in FIGS. 5 (c)-(j) is dependent on the substrate on which the monolayer will be formed. Z=SH for SAMs on gold, platinum, etc. Z=SiCl₃, SiCl₂R′, SiClR′₂, Si(OCH₃)₃, Si(OC₂H₅)₃, GeCl₃, PO(OH)₂, to create monolayers on the gate insulator or substrate materials. In all cases, Z may include an alkyl spacer group between the ring structure and the terminal surface reactive group.

[0059] To achieve optimal ordering of the aromatic organic semiconductors, it is imperative that the SAM terminates with a bond that is parallel to the substrate, and hence to the desired orientation of the depositing semiconductor film. This can be accomplished by using cyclic structures with an odd number of carbon atoms that are attached to the surface through a single point of attachment [FIGS. 5 (a)-(e), (j)], or cyclic structures with an even number of carbon atoms that are attached to the surface through two points of attachment on adjacent ring atoms. See, e.g., (FIGS. 5 (f)-(i)). The ring structures may be saturated or unsaturated, aromatic, or have additional fused rings in addition to those depicted in FIGS. 1 and 5 as long as the additional rings do not change the orientation of the external, or terminal bond. Additional aliphatic groups at R′ are also acceptable as long as they do not disrupt the SAM formation of the molecule.

[0060] Examples of suitable monolayer compounds for insulator and substrate materials include, but are not limited to: 1,1-diethoxy-1-silacyclopent-3-ene, cyclotetramethylenedichlorosilane, cyclopentyltrichlorosilane, (3-cyclopentadienylpropyl)triethoxysilane, and 2,3-naphthalenedicarboxylic acid.

[0061] Examples of suitable monolayers compounds for deposition on electrode materials include, but are not limited to: cyclopentane thiol, 1,2-benzenedithiol, and 2,3-naphthalenedithiol.

[0062] Self-assembled monolayers 18 on the gate insulator (as in FIGS. 2 and 3) or on the substrate (as in FIG. 4) are formed prior to deposition of the organic thin film by subjecting the substrate/insulator to a treatment process that is effective in forming a monolayer containing an appropriate head or binding group on the surface of the substrate/insulator. The substrate/insulator should be freshly cleaned prior to monolayer formation, and preferably by a method that will increase the hydroxyl content of the surface, such as exposure to an oxidizing acid cleaning solution or UV/ozone.

[0063] Specifically, the monolayer 18 is formed by immersing the structure in a silane, germane, carboxylic acid, or phosphonic acid containing solution in an appropriate anhydrous solvent. The monolayer-forming solution may be a concentrated solution or, more preferably, it is a dilute solution in a solvent which completely solubilizes the monolayer-precurser at concentrations up to at least 10-100 millimolar; examples include but are not limited to hexane, toluene, tetrahydrofuran, and acetone. In a highly preferred embodiment, of the present invention, a dilute solution containing from 1-10 millimolar 1,1-diethoxy-1-silacyclopent-3-ene in anhydrous hexane is employed in forming the self-assembled monolayer. The treatment process is carried out at or above room temperature for a time period of about 0.5 to about 48 hours. Elevated temperatures up to 70° C. may be used as long as the elevated temperature does not adversely affect the various layers of the structure. After treatment in the monolayer-forming solution, the structure is removed from the solution, rinsed in pure solvent, and dried. The drying step is typically conducted at a temperature of from about 25° C. to about 100° C. in an inert atmosphere for a time period from about 1 to about 15 minutes. Elevated temperatures may be used to insure that the reactive head groups have completely reacted with the surface.

[0064] Self-assembled monolayers 22 on the electrodes (as in FIGS. 3 and 4) are formed prior to deposition of the organic thin film by subjecting the electrodes to a treatment process that is effective in forming a monolayer of said thiol compounds on the surface of said electrodes. Specifically, the monolayer 22 is formed by immersing the structure in a thiol containing solution. The thiol containing solution may be a concentrated solution or, more preferably, it is a dilute solution in which the thiol compound is dissolved in a solvent such as ethanol or heptane. In a highly preferred embodiment of the present invention, a dilute solution containing from 0.001 to about 0.01% thiol compound in ethanol is employed in forming the self-assembled monolayer. The treatment process is carried out at or above room temperature for a time period of about 0.5 to about 24 hours. After treatment in the thiol solution, the structure is removed from the solution, rinsed in pure solvent, and dried. The drying step is typically conducted at a temperature of from about 25° C. to about 50° C. in an inert atmosphere for a time period from about 1 to about 5 minutes.

[0065] If more than one monolayer is to be deposited on the substrate (as in FIGS. 3 and 4), the monolayer on the electrodes is formed after the monolayer on the substrate/insulator. Once all of the monolayers have been formed, the organic semiconductor material is deposited thereon.

[0066]FIGS. 2, 3, 4, and the above description illustrate three embodiments of the present invention. Other standard thin film transistor structures that are apparent to those skilled in the art can also be used in the present invention. In these other structures, the chemical structure/geometry of the monolayer and its interaction with and ordering of the organic semiconductor distinguishes the present invention from prior art transistor structures.

[0067] Preferred embodiments of the present invention are illustrated in the following Examples.

EXAMPLE 1

[0068] Highly doped silicon wafers with 5000 Å of thermally grown oxide were cleaned using chloroform, UV/ozone, and a heated solution of sulfuric acid and hydrogen peroxide, followed by rinsing and drying. The samples were immersed in 1 millimolar solutions of the following silanes in anhydrous hexane: octadecyltrichlorosilane, phenyltrichlorosilane, cyclopentyltrichlorosilane, cyclotetramethylenedichlorosilane, and 1,1-diethoxy-1-silacyclopent-3-ene, as well as an untreated wafer that was used as a control. The solutions were heated to 50° C., and the samples remained in contact with the silane solution overnight. The samples were rinsed several times in fresh hexane and dried in an inert atmosphere. The samples were baked at 50° C. for 10 minutes to promote the reaction of any unreacted chlorosilane groups. An approximately 300 Å thick film of pentacene was deposited onto the samples through a metal shadow mask using molecular beam deposition techniques. Source and drain electrodes were deposited on top of the organic semiconductor by evaporating gold through a metal mask, producing a device structure similar to that shown in the cross section in FIG. 2.

[0069] The ordering and electrical properties of the organic semiconductor film on these samples was measured by several techniques, including X-ray scattering, atomic force microscopy (AFM), and standard field effect I-V measurements of the transistors, including mobility measurements in the linear and saturation regimes and current on/off ratios. The X-ray scattering data indicates the overall degree of ordering of the pentacene in the film. Highly ordered thin film pentacene will produce sharp (narrow) scattering peaks equivalent to “d” (interlayer) spacings of approximately 15.4 Å, denoted as the (001) spacing (Dimitrakopoulos, C., et.al., J. Appl. Phys., Vol. 80, No. 4, 2501, 1996). Smaller scattering peaks at 7.7 (002), 5.13 (003), and 3.85 (004) are also observable in well ordered films. The X-ray scattering data for these samples is included in FIG. 6. The scattering data indicates that the pentacene forms fairly ordered films when no underlayer is used (the pentacene is deposited on bare SiO₂) (FIG. 6a); a very ordered thin film structure for samples with monolayers of cyclopentanetrichlorosilane (FIG. 6b), cyclotetramethylenedichlorosilane (FIG. 6c), 1,1-diethoxy-1-silacyclopent-3-ene (FIG. 6d), and octadecyltrichlorosilane (OTS)(FIG. 6e)—which is consistent with literature reports on OTS (Jackson, T. N., et.al., IEEE J. of Selected Topics in Quantum Elect., Vol. 4, No. 1, January/February 1998); but there is no observable ordered thin film structure when phenyl silane is used as the underlying monolayer (FIG. 6f).

[0070] The electrical performance of the sample with the phenyl silane monolayer was consistent with the observed difference in the x-ray scattering. The pentacene on the phenyl silane had a mobility of 0.006 cm²V⁻¹sec⁻¹, while those of the samples that had typical scattering patterns for pentacene all had mobilities greater than 0.1 cm²V⁻¹sec⁻¹. The geometry of the phenyl silane appears to have a disruptive influence on the ordering of depositing pentacene, as verified by both the X-ray and electrical measurements.

[0071] The performance of pentacene layers is also affected by the size of the pentacene crystals—with larger crystals (and so fewer grain boundaries) having improved electrical performance. Atomic force microscopy (AFM) was used in the tapping mode to determine the crystal structure of pentacene films deposited on various monolayers. The AFM images are reproduced in FIG. 7. Pentacene deposited on a favorable surface—one that has the terminal ring bond parallel to the surface (as depicted in FIGS. 1 and 5)—will form large, angular, terraced crystal structures, such as those observed for the cyclopentanetrichlorosilane (FIG. 7a), cyclotetramethylenedichlorosilane (FIG. 7b), and 1,1-diethoxy-1-silacyclopent-3-ene (FIG. 7c). These films also had the highest mobilities in both the linear and saturation regimes. The mobilities in the linear regime were 0.35, 0.35, and 0.39 cm²V⁻¹sec⁻¹ respectively, and those in the saturation regime were 0.28, 0.27, and 0.33 cm²V⁻¹sec⁻¹, respectively. Mobilities as high as approximately 1.0 cm²V⁻¹sec⁻¹ have been measured for pentacene on 1,1-diethoxy-1-silacyclopent-3-ene, and it consistently produces devices with mobilities above 0.3 cm²V⁻¹sec⁻¹. A film of pentacene on octadecyltrichlorosilane, which has terminal methyl groups, exhibited somewhat smaller and more dendridic grains (FIG. 7d), and also a smaller mobility of 0.17 cm²V⁻¹sec⁻¹ in the linear regime, and 0.14 cm²V⁻¹sec⁻¹in the saturation regime. Films on phenyl terminated monolayers, such as phenyltrichlorosilane (FIG. 7e), phenyl thiol (FIG. 7f) or anthracene thiol (FIG. 7g), which all have a ring carbon atom rather than a ring bond in the terminal position, produced very small (note the smaller scale for these micrographs) and poorly layered crystals that were consistent with their very poor (almost two orders of magnitude lower mobility) electrical performance. Pentacene deposited on smooth, thermally grown oxide grows relatively large, angular terraced crystals (FIG. 7h), similar to those on the ring structures with terminal parallel bonds, although the mobility was slightly lower, averaging around 0.20-0.37 cm²V⁻¹sec⁻¹ in the linear regime, and 0.14-0.25 cm²V⁻¹sec⁻¹ in the saturation regime. The on/off ratio of the current (Ion/Ioff) was consistently better for the devices where the pentacene was deposited on a SAM than for those on pure SiO₂ surfaces, generally by about an order of magnitude.

EXAMPLE 2

[0072] Bottom contact devices, as depicted in the cross section in FIG. 3, require monolayers to be applied on both the gate insulator and the electrodes to produce a uniform surface for pentacene deposition. In these cases, highly doped silicon wafers with 5000 Å of thermally grown oxide were cleaned using chloroform, UV/ozone, and a heated solution of sulfuric acid and hydrogen peroxide, followed by rinsing and drying. Patterned gold or gold on chromium contacts were deposited by evaporation through a metal shadow mask. Samples were immersed in 1 millimolar solutions of octadecyltrichlorosilane or 1,1-diethoxy-1-silacyclopent-3-ene in anhydrous hexane, and untreated samples were used as controls. The solutions were heated to 50° C., and the samples remained in contact with the silane solution overnight. The samples were rinsed several times in fresh hexane and dried in an inert atmosphere. The samples were baked at 50° C. for 10 minutes to promote the reaction of any unreacted chlorosilane groups. Samples were then placed in 1 millimolar room temperature solutions of either hexadecanethiol or cyclopentylthiol in ethanol. The samples remained in the solution overnight, after which they were rinsed in pure ethanol and dried under a stream of nitrogen. An approximately 300 Å thick film of pentacene was deposited onto the samples through a metal shadow mask using molecular beam deposition techniques, producing a structure similar to that depicted in cross section in FIG. 3.

[0073] The electrical properties of the devices were measured and the mobility of devices with just a thiol monolayer on the electrodes was lower than for samples that had monolayer treatments on both the gate insulator and the electrodes, and those treated with cyclic organic molecules with bonds parallel to the substrate were higher than those with terminal methyl groups. The mobility in the linear regime for samples treated with cyclopentanethiol and cyclopentanetrichlorosilane was 0.24 cm²V⁻¹sec⁻¹, while that for devices treated with hexadecanethiol and octadecanetrichlorosilane was 0.18 cm²V⁻¹sec⁻¹. The mobilities measured in the saturation regime exhibited a similar trend, where the mobility of devices treated with cyclopentanethiol and cyclopentanetrichlorosilane was 0.24 cm²V⁻¹sec⁻¹, while that for devices treated with hexadecanethiol and octadecanetrichlorosilane was 0.20 cm²V⁻¹sec⁻¹. Devices treated with phenylthiol and phenyltrichlorosilane had a mobility of only 1×10⁻⁴ cm²V⁻¹sec⁻¹. For comparison, devices treated with only cyclopentanethiol or hexadecanethiol had mobilities of 0.09 cm²V⁻¹sec⁻¹, and devices devoid of any monolayer treatment exhibited mobilities of 0.05 cm²V⁻¹sec⁻¹.

[0074] The deposition of pentacene is affected by the geometry and structure of the surface onto which it is deposited. Pentacene appears to form the most well-organized and oriented films when it is deposited on substrates that have flat bonds parallel to the surface in the terminal position on a self-assembled monolayer. The worst surface, which produces highly disordered pentacene films that have very poor charge carrier mobility are those that have ring structures with a carbon atom in the ring in the terminal position. Thus, it appears that the geometry of the SAM relative to the depositing pentacene, rather than just the molecular composition of the monolayer is the key factor to achieving improved ordering and performance from deposited organic semiconducting films.

[0075] By practicing the method of the present invention, the following advantages to the conventional solution of transistor fabrication using organic semiconductors have been shown:

[0076] (a) Increased mobility of semiconducting layers of vapor deposited pentacene have been demonstrated on the disclosed cyclic monolayers.

[0077] (b) The measured mobilities of pentacene layers on the disclosed monolayer are more reproducible than on substrates without monolayers or with monolayers having other terminal groups.

[0078] (c) The ratio of the on and off currents is improved and more consistent than on substrates without monolayers or with monolayers having other terminal groups

[0079] While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the appended claims. 

Having thus described our invention in detail, what we claim as new and desire to secure by he Letters Patent is:
 1. A method for improving the performance of an organic thin film transistor comprising the steps of: (a) forming a transistor structure, having as part of its structure, a layer of organic semiconductor that is deposited onto organic surfaces, dielectric surfaces, metal surfaces, or combinations thereof; (b) treating said organic or dielectric surfaces prior to deposition of said layer of organic semiconductor with a compound having the formula: RZ or RZ₂ wherein Z terminates with a functional group capable of binding to and forming a self-assembled monolayer on the surfaces of said organic or insulator surfaces such as chlorosilanes, methoxy or ethoxy silanes, germanium halides, carboxylic acids, or phosphonic acids, and R has a cyclic aromatic or saturated or unsaturated aliphatic ring structure with a geometry that results in the external portion of the molecule terminating in a bond that is parallel to said organic or insulator surfaces when the binding groups (Z) are appropriately attached to said surfaces; (c) treating said metal surfaces, prior to deposition of the organic semiconductor with a compound having the formula: RSH or R(SH)₂ wherein the terminal thiol is capable of binding to and forming a self-assembled monolayer on the metals; and R has a cyclic aromatic or saturated or unsaturated aliphatic ring structure with a geometry that results in the external portion of the molecule terminating in a bond that is parallel to said metal surfaces when the thiols are appropriately attached to said surfaces.
 2. The method of claim 1, wherein the organic semiconductor is deposited over more than one type of material, each said material sequentially treated with the reactive RZ, RZ₂, RSH or R(SH)₂ compound that will bind and form a monolayer onto said surface of the material prior to deposition of said organic semiconductor.
 3. The method of claim 2 wherein said gate insulator is formed surrounding a gate region which is positioned on a surface of a semiconductor substrate
 4. The method of claim 2 wherein said patterned source and drain electrodes are formed on a surface of a gate insulator, and said gate insulator surrounding a gate region which is positioned on a surface of a semiconductor substrate
 5. The method of claim 2 wherein said patterned source and drain electrodes are formed on an exposed surface of a substrate.
 6. The method of claim 2 further comprising forming an organic semiconductor material on a portion of said treated surface, which is a gate insulator, treated substrate, treated source and drain electrodes, or combinations thereof.
 7. The method of claim 6 further comprising forming a gate insulator on top of said organic semiconductor material, and forming a gate on said gate insulator.
 8. The method of claim 6 wherein said organic semiconductor material is a material selected from the group consisting of pentacene, tetracene, and other fused ring organic semiconductors.
 9. The method of claim 8 wherein said organic semiconductor is pentacene.
 10. The method of claim 2 wherein said metal surface is a patterned source and drain electrodes composed of the same or different conductive metal, metal alloy, metal oxide, metal alloy oxide or a stack thereof.
 11. The method of claim 10 wherein said conductive metal is a metal selected from the group consisting of gold, platinum, tungsten, palladium, aluminum, chromium, titanium, and a stack thereof.
 12. The method of claim 11 wherein said conductive metal is gold, chromium, platinum, titanium or a stack thereof.
 13. The method of claim 2 wherein said gate insulator is an inorganic or organic dielectric material that contains oxide or hydroxyl functionality.
 14. The method in claim 13 wherein said inorganic dielectric is SiO₂.
 15. The method of claim 3 wherein said substrate is a Si-containing substrate selected from the group consisting of SiO₂, Si, SiGe, silicon-on-insulator and glass.
 16. The method of claim 3 wherein said substrate is an Al-containing substrate.
 17. The method of claim 3 wherein said substrate is an organic or polymeric material selected from the group consisting of polycarbonate, polyethylene terethalate, polyimide, polyvinyl chloride, nylon, polyethylene, polypropylene, and epoxy.
 18. The method of claim 1 wherein the organic portion of said monolayer forming compound contains an aromatic, saturated or unsaturated aliphatic ring structure with a geometry that requires the external bond of the ring to be parallel to the substrate surface after monolayer formation.
 19. The method of claim 18 wherein the organic portion of said monolayer forming compound is covalently bonded to a functional, or “head” group that can react or strongly interact with organic, oxide, or metal surfaces to form a self-assembled monolayer.
 20. The method of claim 19 wherein the said head group of said monolayer forming compound for said substrate or said gate insulator is a chlorosilane, trimethoxysilane, triethoxysilane, germanium halide, carboxylic acid, or phosphonic acid.
 21. The method of claim 19 wherein said monolayer forming compound is selected from the group consisting of cyclopentanetrichlorosilane, cyclopentenetrichlorosilane, cyclotetramethylenedichlorosilane, 1,1-diethoxy-1-silacyclopent-3-ene, 1,2 benzenedi(trichlorosilane), (3-cyclopentadienylpropyl)triethoxysilane, 2,3 napathalenedicarboxylic acid.
 22. The method of claim 21 wherein said silane is 1,1-diethoxy-1-silacyclopent-3-ene.
 23. The method of claim 19 wherein the said head group of said monolayer forming compound for said source and drain electrodes is a thiol.
 24. The method of claim 23 wherein said monolayer forming thiol is chosen from the group cyclopentanethiol, cyclopentenethiol, cyclotetramethylenethiol, 1,2-benzenedithiol, or 2,3-naphthalenedithiol, 2,3 anthracenedithiol.
 25. The method of claim 24 wherein the thiol is cyclopentanethiol.
 26. The method of claim 2 wherein the surface onto which said organic semiconductor will be deposited is composed of more than one of the materials selected from the group metal electrodes, gate insulator, and organic or inorganic substrate.
 27. The method of claim 26 wherein the surfaces of each of the said materials that compose the substrate onto which the organic semiconductor will be deposited are treated in a sequential fashion with monolayer forming molecules that have head groups that will specifically attach to each of the said materials.
 28. The method of claim 27 wherein the monolayers used to treat said different substrate materials all have the same organic group attached to said material-specific head groups, as in the example of cyclopentanetrichlorosilane and cyclopentanethiol applied sequentially to a substrate surface composed of an SiO₂ gate dielectric and gold source/drain electrodes.
 29. The method of claim 2 wherein a dilute monolayer forming solution is employed in said treating step.
 30. The method of claim 29 wherein said dilute monolayer forming solution contains from about 0.001 to about 0.01% of said monolayer forming compound in an organic solvent.
 31. The method of claim 2 wherein said treating step for the substrate or gate insulator is carried out at a temperature between room temperature and 100° C.
 32. The method of claim 2 wherein said treating step for said source and drain electrodes is carried out at a temperature between room temperature and 100° C.
 33. An organic thin film transistor having an organic semiconductor formed over the substrate, gate dielectric, source/drain electrodes, or a combination thereof, wherein all surfaces on which the organic semiconductor is deposited have a self-assembled monolayer formed thereon, said self-assembled monolayer comprising a compound having the formula: RZ or RZ₂ wherein Z terminates with a functional group capable of binding to and forming a self-assembled monolayer on metals such as a thiol, or on organics or oxides such as a chlorosilane, germanium halide, carboxylic acid, or a phosphonic acid; and R has a cyclic aromatic or aliphatic ring structure with a geometry that results in the external surface of the molecule terminating in a bond that is parallel to the surface when the binding (Z) groups are appropriately attached to the surface.
 34. The organic thin film transistor of claim 33 wherein a gate region is formed above or below said organic semiconductor.
 35. The organic thin film transistor of claim 33 wherein said gate region comprises a gate surrounded by a gate insulator.
 36. The organic thin film transistor of claim 33 wherein said patterned source and drain electrodes are composed of the same or different conductive metal, metal alloy, metal oxide, metal alloy oxide, or a stack thereof.
 37. The organic thin film transistor of claim 36 wherein said conductive metal is a metal selected from the group consisting of gold, platinum, tungsten, palladium, aluminum, chromium, titanium, and a stack thereof.
 38. The organic thin film transistor of claim 33 wherein said conductive metal is gold, chromium, platinum, titanium or a stack thereof.
 39. The organic thin film transistor of claim 33 wherein said organic semiconductor material is a material selected from the group consisting of pentacene, tetracene, or other fused ring organic semiconductors.
 40. The organic thin film transistor of claim 38 wherein said organic semiconductor is pentacene.
 41. The organic thin film transistor of claim 32 wherein said patterned source and drain electrodes are formed on an exposed surface of the substrate or said gate insulator.
 42. The organic thin film transistor of claim 41 wherein said substrate is a Si-containing substrate selected from the group consisting of SiO₂, Si, SiGe, silicon-on-insulator and glass.
 43. The organic thin film insulator of claim 41 wherein said substrate is an Al-containing substrate.
 44. A method for preparing an organic thin film transistor having an organic semiconductor formed over a substrate, gate dielectric, source/drain electrodes or a combination thereof, comprising: 1.) Forming a substrate for organic semiconductor deposition; 2.) Depositing a gate electrode on said substrate and patterning it; 3.) Depositing a gate insulator; 4.) Depositing and patterning source and drain electrodes; 5.) Treating all exposed surfaces with compounds that will form appropriate self-assembled monolayers comprising a compound having the formula: RZ or RZ₂ wherein Z terminates with a functional group capable of binding to and forming a self-assembled monolayer on metals such as a thiol, or on organics or oxides such as a chlorosilane, germanium halide, carboxylic acid, or a phosphonic acid; and R has a cyclic aromatic or aliphatic ring structure with a geometry that results in the external surface of the molecule terminating in a bond that is parallel to the surface when the binding (Z) groups are appropriately attached to the surface; 6.) Depositing the organic semiconductors.
 45. A method for preparing an organic thin film transistor comprising a substrate, gate dielectric, source/drain electrodes and organic semiconductor, or a combination thereof, comprising: 1.) Forming a substrate for organic semiconductor deposition; 2.) Depositing a gate electrode on this substrate and patterning it; 3.) Depositing a gate insulator; 4.) Treating the gate insulator with compounds that will form appropriate self-assembled monolayers comprising a compound having the formula: RZ or RZ₂ wherein Z terminates with a functional group capable of binding to and forming a self-assembled monolayer on metals such as a thiol, or on organics or oxides such as a chlorosilane, germanium halide, carboxylic acid, or a phosphonic acid; and R has a cyclic aromatic or aliphatic ring structure with a geometry that results in the external surface of the molecule terminating in a bond that is parallel to the surface when the binding (Z) groups are appropriately attached to the surface; 5.) Depositing the organic semiconductor; 6.) Depositing and patterning the source and drain electrodes. or,
 46. A method for preparing an organic thin film transistor comprising a substrate, gate dielectric, source/drain electrodes and organic semiconductor, or a combination thereof, comprising: 1.) Forming a substrate for organic semiconductor deposition; 2.) Depositing and patterning source and drain electrodes; 3.) Treating all exposed surfaces with compounds that will form appropriate self-assembled monolayers comprising a compound having the formula: RZ or RZ₂ wherein Z terminates with a functional group capable of binding to and forming a self-assembled monolayer on metals such as a thiol, or on organics or oxides such as a chlorosilane, germanium halide, carboxylic acid, or a phosphonic acid; and R has a cyclic aromatic or aliphatic ring structure with a geometry that results in the external surface of the molecule terminating in a bond that is parallel to the surface when the binding (Z) groups are appropriately attached to the surface; 4.) Depositing organic semiconductors; 5.) Depositing a gate insulator; 6.) Depositing and patterning a gate on said gate insulator. 